Model Generation: Creating new designs

• Carbon generates models directly from your “golden” RTL Verilog, VHDL, or mixed language support
• Models are optimized for high performance
• Cycle-level models are completely coherent with the RTL on every cycle boundary
• Full visibility is supported for rapid debug

Model Validation: Verifying individual HW models

• Eliminate Risk - Debug your models against the original HDL testbench
• Carbon models integrate easily into existing reference test suites to verify cycle accuracy of interfaces:
  • Mentor Modelsim
  • Synopsys VCS
  • Cadence NC-Sim
• One model supporting both environments: cycle-level system model and RTL-level HDL environment

Platform Integration: Assembling the models

• Rapidly assemble virtual prototypes - Integrate with all leading virtual platforms
• High performance integration with leading system/platform environments
  • SoC Designer
  • Platform Architect (CoWare)
  • Mipssim
  • SystemC
  • Many Others…
• Easy integration of legacy RTL IP into cycle-level platform environment
• Replace early system models with accurate cycle models compiled from the actual RTL

Architectural Validation: Verifying the actual design

• Analyze and explore design possibilities – Characterize the actual design implementation
• Carbon enables the use of actual RTL code to drive architectural analysis
• Use existing system modeling environments to validate architectural assumptions
• Explore accurate performance parameters of the actual design implementation
• Verify trade-offs made using abstract system models

Firmware Validation: Verifying the SW components

• Debug software before silicon is available - Validate system integration of hardware and software
• Firmware validation requires both the accuracy and performance of platforms built with cycle-level models
• Virtual platforms are easily deployed to multiple design teams
• Reduces project risk while reducing project time – FW debug provides extra verification of the HW

Model Deployment: Providing system models to your customers

• Empower your design chain - Compile models for secure virtual prototype deployment
• Carbon complied models are based on the actual RTL – guaranteed accuracy
• Reduce debug risk by ensuring that model users don’t make ad-hoc model changes themselves to the model source
• Deliver high-performance protected models to your design-chain customers
• Control exactly how much internal visibility your customers get

© 2008 Carbon Design Systems, Inc. SystemC is a trademark of the Open SystemC Initiative. ARM and RealView are registered trademarks of ARM Limited. Verilog is a registered trademark of Cadence Design Systems. All other trademarks and registered trademarks are the property of their respective owners.