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2006 |
I.Q. Information Quarterly
RTL HW View in the ARM SoC Designer Tool
ESL environments have been held back from wide adoption due to the lack of connection with hardware description languages—Verilog® and VHDL. Legacy IP, 3rd party IP, and new design RTL have sat on the bench. Without a way to import a fast model derived from RTL, users are faced with the daunting task of creating idealized models or waiting until late in the design cycle for a hardware-based solution—FPGAs, emulation, or silicon. |
July 22, 2006 |
EE Times
Replay™ Claims to Break Software Validation Bottleneck
SAN FRANCISCO — According to Carbon (Waltham, Mass.), because ESL simulation environments typically contain models at different levels of abstraction, accuracy and performance, developers validating software on a system model must iterate through all previously validated code to add functionality or debug problems that may have occurred hours into a simulation.The company said its forthcoming Replay feature enables rapid software iterations through validated code and interactive software debug while maintaining cycle-accuracy, removing this performance barrier to incorporating RTL into a heterogeneous modeling environment. |
2006 |
I.Q. Information Quarterly
Getting Practical with ESL Design Methodologies
The advent of extreme fine line processes at 130nm or less presents many challenges. On the back end, optimizing a design to manage physical effects such as power, heat, and timing is more daunting than ever. At the front end, implementing a system-on-chip's (SoC) behavior and features is becoming equally difficult. The early exploration of system architectures is now a critical part of the SoC design process that ensures hardware and software engineers have a well-specified and validated context for their work. Furthermore, the increasing adoption of intellectual property (IP) from multiple sources — legacy, third-party, and newly created — means that systems integration is becoming as significant as the implementation of new design components. |
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